test
---------------------------------------------------- -- VHDL code generated by Visual HDL -- Root of Design: -- --------------- -- Unit Name : recnt -- Library Name : updn8 ---------------------------------------------------- -- Library Name : updn8 -- Unit Name : rotary -- Unit Type : Text Unit ---------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity rotary is port (y,z,clk,A,B : in std_logic ; ud : out std_logic); end; architecture rotary of rotary is begin process (clk) begin if (clk'event and clk = '1') then if ((a = '0' and b = '1' and y = '0' and z = '0') or (a = '1' and b = '1' and y = '0' and z = '1') or (a = '1' and b = '0' and y = '1' and z = '1') or